The Resource Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam
Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam
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The item Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam represents a specific, individual, material embodiment of a distinct intellectual or artistic creation found in University of Missouri-Kansas City Libraries.This item is available to borrow from all library branches.
Resource Information
The item Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam represents a specific, individual, material embodiment of a distinct intellectual or artistic creation found in University of Missouri-Kansas City Libraries.
This item is available to borrow from all library branches.
- Summary
- The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] - [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] - [13] and biomedical [17] -[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] - [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications
- Language
- eng
- Extent
- 1 online resource (58 pages)
- Note
-
- "A thesis in Electrical Engineering."
- Advisor: Masud H Chowdhury
- Vita
- Contents
-
- Introduction
- Next generation high performance device: FinFET
- FinFET based SRAM bitcell designs
- Benchmarking of UF-SRAMs and DTCO-F-SRAMs
- Collaborative project
- Internship experience at INTEL and Marvell Semiconductor
- Conclusion and future work
- Label
- Static random-access memory designs based on different FinFET at lower technology node (7nm)
- Title
- Static random-access memory designs based on different FinFET at lower technology node (7nm)
- Statement of responsibility
- Athiya Nizam
- Language
- eng
- Summary
- The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] - [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] - [13] and biomedical [17] -[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] - [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications
- Cataloging source
- UMK
- http://library.link/vocab/creatorName
- Nizam, Athiya
- Degree
- M.S.
- Dissertation note
- (School of Computing and Engineering).
- Dissertation year
- 2019.
- Granting institution
- University of Missouri-Kansas City,
- Illustrations
- illustrations
- Index
- no index present
- Literary form
- non fiction
- Nature of contents
-
- dictionaries
- bibliography
- theses
- http://library.link/vocab/relatedWorkOrContributorName
- Chowdhury, Masud H.
- http://library.link/vocab/subjectName
-
- Static random access memory
- Field-effect transistors
- Label
- Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam
- Note
-
- "A thesis in Electrical Engineering."
- Advisor: Masud H Chowdhury
- Vita
- Antecedent source
- not applicable
- Bibliography note
- Includes bibliographical references (pages 50-57)
- Carrier category
- online resource
- Carrier category code
-
- cr
- Carrier MARC source
- rdacarrier
- Color
- black and white
- Content category
- text
- Content type code
-
- txt
- Content type MARC source
- rdacontent
- Contents
- Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMs -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future work
- Control code
- 1135982910
- Dimensions
- unknown
- Extent
- 1 online resource (58 pages)
- File format
- one file format
- Form of item
- online
- Level of compression
- mixed
- Media category
- computer
- Media MARC source
- rdamedia
- Media type code
-
- c
- Other physical details
- illustrations.
- Quality assurance targets
- not applicable
- Specific material designation
- remote
- System control number
- (OCoLC)1135982910
- System details
-
- The full text of the thesis is available as an Adobe Acrobat .pdf file; Adobe Acrobat Reader required to view the file
- Mode of access: World Wide Web
- Label
- Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam
- Note
-
- "A thesis in Electrical Engineering."
- Advisor: Masud H Chowdhury
- Vita
- Antecedent source
- not applicable
- Bibliography note
- Includes bibliographical references (pages 50-57)
- Carrier category
- online resource
- Carrier category code
-
- cr
- Carrier MARC source
- rdacarrier
- Color
- black and white
- Content category
- text
- Content type code
-
- txt
- Content type MARC source
- rdacontent
- Contents
- Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMs -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future work
- Control code
- 1135982910
- Dimensions
- unknown
- Extent
- 1 online resource (58 pages)
- File format
- one file format
- Form of item
- online
- Level of compression
- mixed
- Media category
- computer
- Media MARC source
- rdamedia
- Media type code
-
- c
- Other physical details
- illustrations.
- Quality assurance targets
- not applicable
- Specific material designation
- remote
- System control number
- (OCoLC)1135982910
- System details
-
- The full text of the thesis is available as an Adobe Acrobat .pdf file; Adobe Acrobat Reader required to view the file
- Mode of access: World Wide Web
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<div class="citation" vocab="http://schema.org/"><i class="fa fa-external-link-square fa-fw"></i> Data from <span resource="http://link.library.umkc.edu/portal/Static-random-access-memory-designs-based-on/IhU0Xbvf9bg/" typeof="Book http://bibfra.me/vocab/lite/Item"><span property="name http://bibfra.me/vocab/lite/label"><a href="http://link.library.umkc.edu/portal/Static-random-access-memory-designs-based-on/IhU0Xbvf9bg/">Static random-access memory designs based on different FinFET at lower technology node (7nm), Athiya Nizam</a></span> - <span property="potentialAction" typeOf="OrganizeAction"><span property="agent" typeof="LibrarySystem http://library.link/vocab/LibrarySystem" resource="http://link.library.umkc.edu/"><span property="name http://bibfra.me/vocab/lite/label"><a property="url" href="http://link.library.umkc.edu/">University of Missouri-Kansas City Libraries</a></span></span></span></span></div>
