The Resource Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK, Bhavana Tejaswini Repalle

Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK, Bhavana Tejaswini Repalle

Label
Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK
Title
Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK
Statement of responsibility
Bhavana Tejaswini Repalle
Creator
Contributor
Author
Degree supervisor
Subject
Genre
Language
eng
Summary
As the technology node scales down, the coupling capacitance between the adjacent metal lines increases. With an increase in this electrostatic coupling, the unwanted signal interference also increases, which is popularly called as Crosstalk. In conventional circuits, the Crosstalk affects either functionality or performance or both. Therefore the Crosstalk is always considered as detrimental to the circuits, and we always try to filter out the Crosstalk noise from signals. Crosstalk Computing Technology tries to astutely turn this unwanted coupling capacitance into computing principle for digital logic gates[1, 2]. The special feature of the crosstalk circuits is its inherent circuit mechanism to build polymorphic logic gates[3]. Our team has previously demonstrated various fundamental polymorphic logic circuits [1-6,16-18]. This thesis shows the design of the large-scale polymorphic crosstalk circuits such as Multiplier-Sorter, Multiplier-Sorter-Adder using the fundamental polymorphic gates, and also analyzes the Power, Performance, and Area (PPA) for these large-scale designs. Similar to the basic and complex polymorphic gates, the functionality of the large-scale polymorphic circuits can also be altered using the control signals. Owing to their multi-functional embodiment in a single circuit, polymorphic circuits find a myriad of useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. [3]. Also, in this thesis, a lot of studies have been done on the variability (PVT analysis) of Crosstalk Circuits. This PVT variation analysis establishes the circuit design requirements in terms of coupling capacitances and fan-in limitation that allows reliable operation of the Crosstalk gates under Process, Voltage and Temperature variations. As an example, I also elaborate on the reason for which the full adder can't be implemented as a single gate in the crosstalk circuit-style at lower technology nodes. Though we designed a variety of basic and complex logic gates and crosstalk polymorphic gates, the biggest question is "Will these crosstalk gates work reliably on silicon owing to their new circuit requirements and technological challenges?". Trying to answer the above question, the whole thesis is mainly focused on the physical implementation of the crosstalk gates at 65nm. I will detail the steps that we have performed while designing the crosstalk circuits and their layouts, the challenges we faced while implementing the new circuit techniques using conventional design approaches and PDK, and their solutions, specifically during layout design and verification. The other potential application of crosstalk circuits is in non-linear analog circuits: Analog-to-Digital Converter (ADC) [4], Digital-to-Analog Converter (DAC), and Comparator. In this thesis, I have shown how the deterministic charge summation principle that is used in digital crosstalk gates can also be used to implement the non-linear analog circuits
Cataloging source
UMK
http://library.link/vocab/creatorName
Repalle, Bhavana Tejaswini
Degree
M.S.
Dissertation note
(School of Computing and Engineering).
Dissertation year
2019.
Granting institution
University of Missouri-Kansas City,
Illustrations
illustrations
Index
no index present
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
  • theses
http://library.link/vocab/relatedWorkOrContributorName
Rahman, Mostafizur
http://library.link/vocab/subjectName
Crosstalk
Label
Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK, Bhavana Tejaswini Repalle
Instantiates
Publication
Copyright
Note
  • "A thesis in Computer and Electrical Engineering."
  • Advisor: Mostafizur Rahman
  • Vita
Antecedent source
not applicable
Bibliography note
Includes bibliographical references (pages 54-56)
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
black and white
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Introduction -- Polymorphic Crosstalk circuit design -- Practical realization of Crosstalk circuits -- PVT variation analysis -- Difficulties or errors in layout design and full chip details -- Potential miscellaneous applications -- Conclusion and future work
Control code
1135866748
Dimensions
unknown
Extent
1 online resource (57 pages)
File format
one file format
Form of item
online
Level of compression
mixed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
illustrations.
Quality assurance targets
not applicable
Specific material designation
remote
System control number
(OCoLC)1135866748
System details
  • The full text of the thesis is available as an Adobe Acrobat .pdf file; Adobe Acrobat Reader required to view the file
  • Mode of access: World Wide Web
Label
Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK, Bhavana Tejaswini Repalle
Publication
Copyright
Note
  • "A thesis in Computer and Electrical Engineering."
  • Advisor: Mostafizur Rahman
  • Vita
Antecedent source
not applicable
Bibliography note
Includes bibliographical references (pages 54-56)
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
black and white
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Introduction -- Polymorphic Crosstalk circuit design -- Practical realization of Crosstalk circuits -- PVT variation analysis -- Difficulties or errors in layout design and full chip details -- Potential miscellaneous applications -- Conclusion and future work
Control code
1135866748
Dimensions
unknown
Extent
1 online resource (57 pages)
File format
one file format
Form of item
online
Level of compression
mixed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
illustrations.
Quality assurance targets
not applicable
Specific material designation
remote
System control number
(OCoLC)1135866748
System details
  • The full text of the thesis is available as an Adobe Acrobat .pdf file; Adobe Acrobat Reader required to view the file
  • Mode of access: World Wide Web

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